Verilog error: not a valid l-value
I'm trying to test if a wire(s) is on or not to signify if there is an error/overflow in my alu code. Given this code:
output reg[3:0]x; // line 149 output wire error; output wire overflow; always @* begin if(error || overflow) begin assign x = 4'b1111; // line 155 assign error = ~error; assign overflow = ~overflow; end else begin assign x = opcode; end end
I get following error messages:
uut is my instantiation unit in my testbench called
Your using the assign incorrectly. That can be used outside of a always process, but not inside of one.
Also, the type wire, is required for an assign
wire [3:0] x; assign x = 4'b1111;
Inside the always process, remove the assign statement and just say
reg [3:0] x; // Note that this is assigned as a reg now always @* begin if(blah) begin x = 4'b1111; end else begin x = opcode; end end
The code in the example has several issues.
1) you tried to use 'procedural assignments' which is an advanced verilog topic. In other words
assignstatement inside of an
alwaysblock. This is not synthesizable, can only be used on
regtypes, and is there in verilog for very special cases. Do not use it.
You error messages coming from the fact that
overfloware declared as
2) you are trying to assign inverted version of a value to itself in a non-clocked logic. It will not behave the way you expect. Depending on usage it can either not toggle or will cause an infinite zero-delay loop, or in your case it could just generate a glitch.
So, potentially, your code should look something like the following:
input wire clk; // << you need clock output reg[3:0]x; // line 149 output wire error; output wire overflow; reg error_reg, overflow_reg; always @(posedge clk) begin if(error || overflow) begin x <= 4'b1111; // line 155 error_reg <= ~error; overflow_reg <= ~overflow; end else begin x <= opcode; end assign error = error_reg; assign overflow = overflow_reg; end