# Taylor Series in Verilog

I am doing my first student Project in Verilog. My project is to calculate log base 2 using "Taylor Series" in Fixed-Point arithmetic (s4.27). I have implemented the Horner's method as well in my code.

Overall it looks like this:

log=c0+(q*(c1+(q*(c2+(q*(c3+(q*(c4(q*(c5+(q*c6))))))))));


Finally log_base_2=log*con;

timescale 10ns/10ns

module log (q ,clk,log_result);

input clk;
input [31:0] q; // q=x-a; x=user input, a=1.5 (Taylor series is calculated around point "a")

output [31:0] log_result;

localparam con= 32'h0B8AA3B0; //1.44269504088895
localparam c0 = 32'h033E647C; //0.40546510810816
localparam c1 = 32'h05555558; //0.66666666666666
localparam c2 = 32'hFE38E38E; //-0.222222222222
localparam c3 = 32'h00CA4588; //0.0987654321
localparam c5 = 32'h0035F068; //0.02633744856
localparam c6 = 32'hFFE208AA; //-0.01463191587

wire [31:0] x0,x1,x2,x3,x4,x5,x6;
wire [31:0] y0,y1,y2,y3,y4,y5,y6;

multiplier  #(27,32) m6(.i_multiplicand(q),.i_multiplier(c6),.o_result(x6));
multiplier  #(27,32) m5(.i_multiplicand(q),.i_multiplier(y6),.o_result(x5));
multiplier  #(27,32) m4(.i_multiplicand(q),.i_multiplier(y5),.o_result(x4));
multiplier  #(27,32) m3(.i_multiplicand(q),.i_multiplier(y4),.o_result(x3));
multiplier  #(27,32) m2(.i_multiplicand(q),.i_multiplier(y3),.o_result(x2));
multiplier  #(27,32) m1(.i_multiplicand(q),.i_multiplier(y2),.o_result(x1));
multiplier  #(27,32) (.i_multiplicand(con),.i_multiplier(y1),.o_result(x0));

assign log_result = x0;

endmodule


Test bench code:

timescale 10ns/10ns

module tb_log ();

reg clk;
reg [ 31 : 0 ] q;

wire [ 31 : 0 ] log_result;

log log_i (
.q(q),
.clk(clk),
.log_result(log_result)
);

parameter CLKPERIODE = 100;

initial clk = 1'b1;
always #(CLKPERIODE/2) clk = !clk;

initial begin

$dumpfile("log_wave.vcd");$dumpvars(1);

$monitor ("Q=%h,Log2=%h ", q, log_result); #1 #(CLKPERIODE) q = 32'hFC000000; // q=1-1.5=-0.5;$finish();

end

endmodule


So I am expecting a result close to zero. But unfortunately I am getting 9B917CED. When I tried to include clock an error naming "Malformed Statement" occurred. I am using Icarus verilog for compiling.

I am sure there are bugs but currently my rookie eyes are unable to notice it. What am I missing?