Verilog nested for loop in testbench no iterating correctly

Good evening,

I designed a structural design of the MC14585B magnitude comparator: https://www.onsemi.com/pub/Collateral/MC14585B-D.PDF

I wanted to simulate all 2^8 possibilities and so I wrote a testbench to just that. I am using modelsim student edition:

source:

module MC14585(
    input [3:0] A, B,
    input A_less_B_in, A_greater_B_in, A_equal_B_in,
    output A_less_B_out, A_greater_B_out, A_equal_B_out);

    wire [3:0] exor, not_A, not_B, nand1, or1;
    wire not_A_less_B_in, not_A_equal_B_in, nand2, nor1;

    not n1(not_A_less_B_in, A_less_B_in);
    not n2(not_A_equal_B_in, A_equal_B_in);

    xor x1(exor[0], A[0], B[0]);
    xor x2(exor[1], A[1], B[1]);
    xor x3(exor[2], A[2], B[2]);
    xor x4(exor[3], A[3], B[3]);

    not n3(not_A[0], A[0]);
    not n4(not_A[1], A[1]);
    not n5(not_A[2], A[2]);
    not n6(not_A[3], A[3]);

    not n7(not_B[0], B[0]);
    not n8(not_B[1], B[1]);
    not n9(not_B[2], B[2]);
    not n10(not_B[3], B[3]);

    nand na1(nand1[0], not_A[0], B[0]);
    nand na2(nand1[1], not_A[1], B[1]);
    nand na3(nand1[2], not_A[2], B[2]);
    nand na4(nand1[3], not_A[3], B[3]);

    or o1(or1[0], exor[3], exor[2], exor[1], exor[0], not_A_less_B_in);
    or o2(or1[1], exor[3], exor[2], exor[1], nand1[0]); 
    or o3(or1[2], exor[3], exor[2], nand1[1]);
    or o4(or1[3], exor[3], nand1[2]);

    nand na5(nand2, or1[0], or1[1], or1[2], or1[3], nand1[3]);
    nand na6(A_less_B_out, or1[0], or1[1], or1[2], or1[3], nand1[3]);

    nor not_or1(nor1, exor[0], exor[1], exor[2], exor[3], not_A_equal_B_in);
    nor not_or2(A_greater_B_out, nand2, nor1);

endmodule

testbench:

`timescale 1ns / 1ps

module Assignment1_tb();
    reg[3:0] A, B;
    wire A_less_B, A_greater_B, A_equal_B;

    MC14585 MC14585_DUT(
        .A(A),
        .B(B),
        .A_less_B_in(1'b0),
        .A_greater_B_in(1'b0),
        .A_equal_B_in(1'b1),
        .A_less_B_out(A_less_B),
        .A_greater_B_out(A_greater_B),
        .A_equal_B_out(A_equal_B));

    initial begin   
        for (A = 0; A < 16; A=A+1) begin
            for (B = 0; B < 16; B=B+1) begin

                if (A_less_B && (A < B))
                    $display ("%d is less than %d", A, B);
                else if (A_greater_B && (A > B))
                    $display ("%d is greater than %d", A, B);
                else if (A_equal_B && (A == B))
                    $display ("%d is equal to %d", A, B);
                else
                    $display ("ERROR"); 

                #10;    
            end
        end
    end
endmodule

For some reason when I run my testbench, the outer for loop (A) doesn't iterate values at all. Also, I placed this loop into an initial statement so it will only iterate all the way through once, but it continues to run until I end the simulation.

Here is some sample output:

#  0 is less than  2
#  0 is less than  3
#  0 is less than  4
#  0 is less than  5
#  0 is less than  6
#  0 is less than  7
#  0 is less than  8
#  0 is less than  9
#  0 is less than 10
#  0 is less than 11
#  0 is less than 12
#  0 is less than 13
#  0 is less than 14
#  0 is less than 15
# ERROR
# ERROR
#  0 is less than  2
#  0 is less than  3
#  0 is less than  4
#  0 is less than  5
#  0 is less than  6
#  0 is less than  7
#  0 is less than  8
#  0 is less than  9
#  0 is less than 10
#  0 is less than 11
#  0 is less than 12
#  0 is less than 13
#  0 is less than 14
#  0 is less than 15
# ERROR
# ERROR
#  0 is less than  2
#  0 is less than  3
#  0 is less than  4
#  0 is less than  5
#  0 is less than  6
#  0 is less than  7
#  0 is less than  8
#  0 is less than  9

any ideas what's going on? Thanks

1 answer

  • answered 2018-02-13 02:07 Serge

    Your problem is in these statements:

       reg[3:0] A, B;
       ...
       for (B = 0; B < 16; B = B + 1)
    

    since B is '4' bits wide, it will never be greater or equal to 16. When it gets 15 (4'b1111), the next increment will overflow and make it '0'.

    You need make B wider than 4 bits.