Can I repeat modules in other module on system-Verilog?

module multp(  
    input logic clk, start,
    input logic [3:0] in1,
    input logic [7:0] in2,
    output logic fin,
    output logic [8:0] out1);

    logic [7:0] x2add, p2add, add2p;
    wire logic x_shl, x_l, y_l, y_shr, ylsb, add;
    wire logic p_l, p_clr, cnt_clr, cnt_inc, done;

    xreg xreg1( clk, x_shl, x_l, in1, x2add);
    yreg yreg1( clk, y_shr, y_l, in2, ylsb);
    adder adder1( add, p2add ,x2add ,add2p);
    preg preg1( clk, p_l, p_clr, add2p, p2add);
    cnt cnt1( clk, cnt_clr, cnt_inc, done );
    cu cu1( clk, start, done, ylsb, finish, x_load, x_shl, add, p_load, p_clr, y_load, y_shr, cnt_clr, cnt_inc);

    always_ff @ (posedge clk)
        begin
            out1 <= p2add;
        end
endmodule

above code is what I did and wanted to do. I just wanted to repeat insided modules with clock signal but when I put always statement ahead those modules, there's some syntax error with not a task or void function

and this is the test bench.

module multp_tb();
    reg clk, start;
    reg [3:0] in1;
    reg [7:0] in2;
    wire fin;
    wire [8:0] out1;

multiplier uut(
    .clk(clk),
    .start(start),
    .in1(in1),
    .in2(in2),
    .finish(finish),
    .out1(out1)
);

always begin
    clk=~clk;
    #50;
end

initial begin
    clk=0; start=0; in1=4'b0001; in2=8'b00000001; 
    #100;
    start=1;
    #100;
    start=0;    
end

endmodule

and the sample module of my modules is like

module cnt(
    input logic clk, cnt_clr, cnt_inc,
    output logic done);

    reg [2:0] temp;

    always_ff@(posedge clk)
        begin 
            if (cnt_clr) temp <=3'b000;
            else if (cnt_inc) temp<=temp+1;
        done <= temp[2];
        end
endmodule

But all modules were simulated once not even twice.

Is there any way to repeat these modules so that I can see my simulate this module operated with clock?