what are the uses of case 'inside's in verilog ? is it synthesizable?

in verilog, we have case 'inside's. what are the usages of that & is it synthesizable?

eg :

case(in) inside
  4'b0000, 4'b00?1: ; // 0 and 1,3
  [5:7]: ; // 5,6,7
  default: ;
endcase

1 answer

  • answered 2019-08-13 07:48 Matthew Taylor

    In Verilog you don't have case inside - that is SystemVerilog. In Verilog, if you want wildcards in your case statement, you have to use either casez or casex. In a casez statement, a Z means don't care; in a casex statement, a Z or an X means don't care, eg

    casez (in)
      4'b0000, 4'b00z1: ; // 0 and 1,3
      4'b0101, 4'b0110, 4'b0111: ; // 5,6,7
      default: ;
    endcase
    

    or, because a ? is an exact synonym for Z:

    casez (in)
      4'b0000, 4'b00?1: ; // 0 and 1,3
      4'b0101, 4'b0110, 4'b0111: ; // 5,6,7
      default: ;
    endcase
    

    or, with casex:

    casez (in)
      4'b0000, 4'b00x1: ; // 0 and 1,3
      4'b0101, 4'b0110, 4'b0111: ; // 5,6,7
      default: ;
    endcase
    

    SystemVerilog added case inside, which is better, because it allows ranges to be used (like in your original example):

      [5:7]: ; // 5,6,7
    

    and because it is asymmetrical. Using casex is the second biggest sin in Verilog (second to using ordered port mapping). This is because casex is symmetrical (as is casez). By this, I mean that with casex an X in the input expression (in in your example) also means don't care, which means that if the input expression goes to X then all branches match (and the first is executed because the first matching branch is executed in a Verilog case statement). The result of this is that if a net or variable goes to X, casex will filter it out rather than propagating it, which means a bug might get hidden. This does not happen with case inside, because an X (or Z) in the input expression does not mean don't care (that's what I mean by it being asymmetrical).

    So, you would use case inside anywhere you want a case statement with wildcards or ranges. And yes - it is synthesisable.


    casez is considered safer in Verilog, because it is unlikely that an input expression would spuriously go to Z.