what are the uses of case 'inside's in verilog ? is it synthesizable?
in verilog, we have case 'inside's. what are the usages of that & is it synthesizable?
case(in) inside 4'b0000, 4'b00?1: ; // 0 and 1,3 [5:7]: ; // 5,6,7 default: ; endcase
In Verilog you don't have
inside- that is SystemVerilog. In Verilog, if you want wildcards in your
casestatement, you have to use either
casex. In a
Zmeans don't care; in a
Xmeans don't care, eg
casez (in) 4'b0000, 4'b00z1: ; // 0 and 1,3 4'b0101, 4'b0110, 4'b0111: ; // 5,6,7 default: ; endcase
or, because a
?is an exact synonym for
casez (in) 4'b0000, 4'b00?1: ; // 0 and 1,3 4'b0101, 4'b0110, 4'b0111: ; // 5,6,7 default: ; endcase
casez (in) 4'b0000, 4'b00x1: ; // 0 and 1,3 4'b0101, 4'b0110, 4'b0111: ; // 5,6,7 default: ; endcase
inside, which is better, because it allows ranges to be used (like in your original example):
[5:7]: ; // 5,6,7
and because it is asymmetrical. Using
casexis the second biggest sin in Verilog (second to using ordered port mapping). This is because
casexis symmetrical (as is
casez). By this, I mean that with
Xin the input expression (
inin your example) also means don't care, which means that if the input expression goes to
Xthen all branches match (and the first is executed because the first matching branch is executed in a Verilog
casestatement). The result of this is that if a net or variable goes to
casexwill filter it out rather than propagating it, which means a bug might get hidden. This does not happen with
inside, because an
Z) in the input expression does not mean don't care (that's what I mean by it being asymmetrical).
So, you would use
insideanywhere you want a
casestatement with wildcards or ranges. And yes - it is synthesisable.
casezis considered safer in Verilog, because it is unlikely that an input expression would spuriously go to