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              POPF  
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  After editing qemu/target/riscv/insn32.decode with a free opcode (following Ashling tutorial), and implementing translator function in insn_trans/trans_rvi.c.inc - QEMU hangs when calling the function as an .insn directive (I know this to work - ). Changing opcodes of existing instructions to test if disassembly changes indicated to me that QEMU was not registering the changes I made and that I didn't rebuild/recompile QEMU correctly. I simply ran make clean, reconfigured and make again in the QEMU directory to rebuild it - Is this the correct way to rebuild QEMU in this toolchain or is there something I missed.

  The code to call

  #include <stdio.h>
  
  
  static int test_ins(int a, int b) {
          int result;
          asm volatile(".insn r 0x33, 7, 0x20, %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
          return result;
  }
  
  
  int main() {
          int a, b, result;
          a = 2;
          b = 4;
          result = test_ins(a,b);
          printf("%d\n", result);
  }
  

  Instruction in insn32.decode is as follows:

  OPCODE = "0110011", FUNCT3 = "111" and FUNCT7 = "0100000".
  

  Implementation of aforementioned instruction is as follows:

  static bool trans_bitcnt(DisasContext *ctx, arg_bitcnt *a)
  {
  TCGLabel *loop_source1 = gen_new_label();
  TCGLabel *loop_source2 = gen_new_label();
  TCGv source1, source2, dstval, cntval;
  source1 = tcg_temp_local_new();
  source2 = tcg_temp_local_new();
  dstval = tcg_temp_local_new();
  cntval = tcg_temp_local_new();
  // Count all the bits set in rs1 and rs2 and put that number in rd
  gen_get_gpr(source1, a->rs1);
  gen_get_gpr(source2, a->rs2);
  tcg_gen_movi_tl(cntval, 0x0);
  /* Count the bits that are set in the first register */
  gen_set_label(loop_source1);
  tcg_gen_andi_tl(dstval, source1, 0x1);
  tcg_gen_shri_tl(source1, source1, 0x1);
  tcg_gen_add_tl(cntval, cntval, dstval);
  tcg_gen_brcondi_tl(TCG_COND_NE, source1, 0x0, loop_source1);
  /* Count the bits that are set in the second register */
  gen_set_label(loop_source2);
  tcg_gen_andi_tl(dstval, source2, 0x1);
  tcg_gen_shri_tl(source2, source2, 0x1);
  tcg_gen_add_tl(cntval, cntval, dstval);
  tcg_gen_brcondi_tl(TCG_COND_NE, source2, 0x0, loop_source2);
   /* Update the destination register with the bits total */
  gen_set_gpr(a->rd, cntval);
  tcg_temp_free(source1);
  tcg_temp_free(source2);
  tcg_temp_free(dstval);
  tcg_temp_free(cntval);
  return true;
  }
  
• [risc-v]does 2-way Simultaneous multithreading core share register files, or do they have separate registers?

  For example, in an 4-core system with 2-way SMT, you have 8 harts, which is it? 4 separate x0-x31 registers ,pc, and csrs, or 8 separate x0-x31, pc, and csrs?
• Reading RISC-V CSR registers using C asm

  I'm trying to read a csr register using function macro

  I have a struct array that contains name and address of csr registers

  typedef struct csr_lists
  {
      int address;
      const cahr* name;
  } csr_lists;
  
  csr_lists list[] = 
  {
      {0xc00, "CYCLE"},
      ...
  };
  

  And the function I made:

  #define csr_read(csr)                               \
  ({                                                  \
      register uint32_t v;                            \
      __asm__ __volatile__ ("csrr %0, %1"             \
                    : "=r" (v)                        \
                    : "n" (csr)                       \
                    : "memory");                      \
      v;                                              \
  })
  

  So it is called like uint64_t value = csr_read(list[i].address); or uint64_t value = csr_read(0xc00);

  And the compiler gives me following errors

  csr.h:68:2: error: asm operand 1 probably doesn’t match constraints [-Werror]
     68 |  __asm__ __volatile__ ("csrr %0, %1"    \
        |  ^~~~~~~
  csr.c:127:25: note: in expansion of macro ‘csr_read’
    127 |         value[i] = csr_read(list[i].address);
        |  
  csr.h:68:2: error: impossible constraint in ‘asm’
     68 |  __asm__ __volatile__ ("csrr %0, %1"    \
        |  ^~~~~~~
  csr.c:127:25: note: in expansion of macro ‘csr_read’
    127 |         value[i] = csr_read(list[i].address);
        |   
  cc1: all warnings being treated as errors
  /mnt/d/project/riscv32-linux/buildroot-2021.02.10/output/host/lib/gcc/riscv32-buildroot-linux-gnu/9.4.0/../../../../riscv32-buildroot-linux-gnu/bin/ld: ./libhpm.so: undefined reference to `csr_read'
  

  How can I fix this problem?

  edit) The problem happens at these lines

  #define MAX    7
  for (i = 0; i < MAX; i++)
  {
      value[i] = csr_read(list[i].address);
  }